1. Field of the Invention
The present invention relates to a method for producing a semiconductor device, more specifically, to a method for producing a semiconductor device in which a CMOSFET having a lightly doped drain (LDD) structure and a double-diffused MOSFET (DMOS) are integrated on a same semiconductor substrate.
2. Description of the Prior Art
A MOSFET is known to have a current injected into a gate oxide film and a current flowing through a substrate, in addition to a current flowing through a channel. So-called hot carriers participate in the generation of these currents. Electrons as the hot carriers travel in an electric field E which is defined as E=V.sub.DS /L.sub.eff. Therefore, when the value of the voltage V.sub.DS between the source and the drain is constant, the electric field E increases and the hot carriers gain a high energy as an effective channel length L.sub.eff becomes smaller. In a MOSFET with the effective channel length L.sub.eff of 1 .mu.m or less the electric field becomes up to about 10.sup.5 V/cm in the vicinity of the drain. It is unfavorable for the characteristics of the device that the hot carriers flow in the strong electric field. Various structures are proposed to reduce variations in characteristics of the device due to the hot carriers. Basically, these proposed structures relax the electric field in the vicinity of the drain and reduce the substrate current. Ordinary MOSFETs have a drain with high impurity concentrations, and in most MOSFETs, the electric field is considerably concentrated in the vicinity of the drain, and a large amount of the hot carriers is generated, which tend to degrade the characteristics of the MOSFET.
To reduce the generation of the hot carriers, it is preferable to reduce the dopant concentration of the drain, thereby preventing the electric field from concentrating. As one of the methods for this purpose, there has been known as a lightly doped drain structure (S. Ogura et al, "Design and Characteristics of the Lightly Doped Drain-Source (LDD) Insulated Gate Field-Effect Transistor," IEEE Transactions on Electron Devices, vol.ED-27, No. 8 (1980) 1359-1367). In a MOSFET of this type, as compared with ordinary MOSFETs, the substrate current is reduced by a factor of 1-2 figures, and the gate current is reduced by a factor of 3-4 figures, to almost undetectable levels. Furthermore, the drain withstanding voltage under a condition where a drain current is flowing is remarkably improved, achieving a withstanding voltage for satisfactory operation even with a MOSFET having a channel length of 1 .mu.m.
FIGS. 1A to 1F are schematic cross sectional views showing CMOSFET production processes to form an LDD structure having such characteristics.
The left side 10 and the right side 20 in FIGS. 1A to 1F are the regions where a P-channel MOSFET and an N-channel MOSFET are respectively formed.
First, an N-well 21 and a P-well 31 are formed in a silicon substrate 1 to separate the substrate into a P-channel MOSFET region and an N-channel MOSFET region. Then, a thin gate oxide film 41 and a thick field oxide film 42 are formed on the surface of these wells, and polycrystalline silicon is deposited on the gate oxide film 41 and patterned to form gates 51 and 52 (FIG. 1A).
Then, to form source-drain regions of the N-channel MOSFET in the region 10, a resist film 6 is formed by using a photomask, and by using the resist film 6 and the gate 52 as a photomask is implanted in a region 22 a donor ion such as .sup.31 P.sup.+ under the conditions of an acceleration voltage of 50 kV and an implantation amount of 3.times.10.sup.13 /cm.sup.2 (FIG. 1B).
After that, the resist film 6 is removed and an oxide film 43 as a side wall is formed on the side portions of the gates 51 and 52 (FIG. 1C).
Further, the resist film 6 is formed in the region 10 by using a photomask, and by using the gate 52 and the oxide film 43 as a mask a donor ion 72 such as As.sup.+ is implanted in a region 23, which is narrower than the region 22, under the conditions of an acceleration voltage of 50 kV and an implantation amount of 5.times.10.sup.15 /cm.sup.2 (FIG. 1D).
Then, after the resist film 6 is removed, to form the source-drain regions of the P-channel MOSFET in the region 10, the resist film 6 is formed only in the region 20 by using a photomask, and by using the resist film 6, the gate 51, and the oxide film 43 as a mask an acceptor ion 73 such as BF.sub.2.sup.+ is implanted in a region 32 under the conditions of an acceleration voltage of 50 kV and an implantation amount of 3.times.10.sup.15 /cm.sup.2 (FIG. 1E).
After that, the resist film 6 is removed, followed by heat treatment, to form a short channel portion between the N.sup.- regions 22 doped with a low-concentration of .sup.31 P. At the same time, the source-drain regions 23 doped with a high-concentration of As are formed outside the N.sup.- regions 22. Thus, the N-channel MOSFET of an LDD structure is formed. On the other hand, a P-channel MOSFET having the P.sup.+ source-drain regions 32 doped with .sup.11 B is formed in the region 10 (FIG. 1F).
However, there are some problems in the formation of a CMOSFET having LDD structure and the N-channel double-diffused MOSFET (DMOSFET) on the same silicon substrate 1. FIG. 2 shows a part of the N-channel DMOSFET. When implanting acceptor ions and donor ions by using a gate 53 consisting of polycrystalline silicon formed on the surface of the silicon substrate 1 via the oxide film 41 and the oxide film 43 at the side wall of the gate 53 as a mask and heat treating to form a P base region 34 and an N.sup.+ source-drain regions 24 as shown in FIG. 2, if a width W.sub.1 of the oxide film 43 is 0.2 .mu.m and a depth d of the N.sup.+ region 24 is 0.2 .mu.m, a diffusion width W.sub.2 in the lateral direction of the N.sup.+ region 24 becomes 0.16 .mu.m. In such a condition, an inversion layer 45 formed under the gate 53 will not reach the N.sup.+ region 24, and will not be able to operate the N-channel DMOSFET. To solve the problem, when the source-drain regions of the N-channel DMOSFET and the P base region 34 are formed independently from each other by different processes, two additional mask processes are required, resulting in increased production time and cost.